Liquid crystal display and method of manufacturing the same

ABSTRACT

A display apparatus includes a first substrate including pixels, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. Each of the pixels includes a thin film transistor disposed on a first insulating substrate, a first protective layer that covers the thin film transistor and includes a SiOC layer, a first electrode disposed on the first protective layer, a second protective layer that covers the first electrode, and a second electrode disposed on the second protective layer.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority to Korean Patent Application No.10-2012-0037507, filed on Apr. 10, 2012, the entire contents of whichare herein incorporated by reference.

TECHNICAL FIELD

The disclosure relates to a liquid crystal display and a method ofmanufacturing the same. More particularly, the disclosure relates to aPLS (plane-to-switching) mode liquid crystal display and a method ofmanufacturing the PLS mode liquid crystal display.

DISCUSSION OF THE RELATED ART

Liquid crystal displays are flat display apparatuses that display imagesusing a liquid crystal layer. Liquid crystal displays may be classifiedinto in-plane-switching (IPS) mode liquid crystal displays, verticalalignment (VA) mode liquid crystal displays, and plane-to-switching(PLS) mode liquid crystal displays according to a method of driving theliquid crystal layer.

The PLS mode liquid crystal displays drive the liquid crystal layer anddisplay images using a horizontal electric field and a vertical electricfield. In the PLS mode driving scheme, a fringe electric field resultsin rotation of liquid crystal molecules of the liquid crystal layer overan electrode in a direction which is substantially in parallel with asubstrate.

SUMMARY

The present disclosure provides a liquid crystal display that can removeafterimages and reduce signal interference and a method of manufacturingthe liquid crystal display.

An embodiment of the inventive concept provides a liquid crystal displayincludes a first substrate that includes a plurality of pixels, a secondsubstrate facing the first substrate, and a liquid crystal layerinterposed between the first substrate and the second substrate.

At least one of the pixels includes a thin film transistor disposed on afirst insulating substrate, a first protective layer that covers thethin film transistor and includes a SiOC layer, a first electrodedisposed on the first protective layer, a second protective layer thatcovers the first electrode, and a second electrode disposed on thesecond protective layer.

An embodiment of the inventive concept provides a method ofmanufacturing a liquid crystal display including a first substrateincluding a plurality of pixels, a second substrate facing the firstsubstrate, and a liquid crystal display interposed between the first andsecond substrates is provided as follows. A thin film transistor isformed on a first insulating substrate, and a first protective layerincluding a SiOC layer is formed to cover the thin film transistor. Whena first electrode is formed on the first protective layer, a secondprotective layer is formed to cover the first electrode and a secondelectrode is formed on the second protective layer.

According to an embodiment of the present invention, there is provided adisplay apparatus including a plurality of data lines, an SiOC layer onthe plurality of data lines, a common electrode on the SiOC layer, aprotective layer on the common electrode, and a pixel electrode on theprotective layer. The display apparatus may further include a cappinglayer between the SiOC layer and the common electrode. The displayapparatus may further include a buffer layer between the plurality ofdata lines and the SiOC layer. The SiOC layer may have a thickness ofabout two micrometers to about three micrometers.

According to the embodiments of the present invention, since the firstprotective layer includes the SiOC layer having a thickness equal to orlarger than two micrometers, the common electrode and signal linesdisposed under the common electrode may be sufficiently spaced apartfrom each other, thereby preventing signal interference from occurring.

In addition, the SiOC layer has superior heat resistance when comparedwith an organic layer, and thus the SiOC layer may be formed through ahigh temperature process. Thus, a deterioration of display quality,which is caused by the afterimage, may be prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

The embodiments of the present invention will become readily apparent byreference to the following detailed description when considered inconjunction with the accompanying drawings wherein:

FIG. 1 is a block diagram showing a PLS mode liquid crystal displayaccording to an exemplary embodiment of the invention;

FIG. 2 is a view showing a pixel as shown in FIG. 1;

FIG. 3 is a plan view showing a liquid crystal display panel accordingto an exemplary embodiment of the invention;

FIG. 4 is a cross-sectional view taken along a line I-I′ shown in FIG.3;

FIG. 5A to FIG. 5D are plan views showing a process of manufacturing afirst substrate;

FIG. 6A to FIG. 6K are cross-sectional views showing a process ofmanufacturing a first substrate;

FIG. 7 is a cross-sectional view showing a liquid crystal display panelaccording to an exemplary embodiment of the invention; and

FIG. 8 is a cross-sectional view showing a liquid crystal display panelaccording to an exemplary embodiment of the invention.

DETAILED DESCRIPTION

It will be understood that when an element or layer is referred to asbeing “on”, “connected to” or “coupled to” another element or layer, itcan be directly on, connected or coupled to the other element or layeror intervening elements or layers may be present. Like numbers may referto like or similar elements throughout the specification and thedrawings. The present invention may be embodied in various differentways and should not be construed as limited to the exemplary embodimentsdescribed herein. As used herein, the singular forms, “a”, “an” and“the” are intended to include the plural forms as well, unless thecontext clearly indicates otherwise.

As will be appreciated by one skilled in the art, embodiments of thepresent invention may be embodied as a system, method, computer programproduct, or a computer program product embodied in one or more computerreadable medium(s) having computer readable program code embodiedthereon. The computer readable program code may be provided to aprocessor of a general purpose computer, special purpose computer, orother programmable data processing apparatus. The computer readablemedium may be a computer readable signal medium or a computer readablestorage medium. The computer readable storage medium may be any tangiblemedium that can contain, or store a program for use by or in connectionwith an instruction execution system, apparatus, or device.

Hereinafter, the embodiments of the present invention will be describedin detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a PLS mode liquid crystal displayaccording to an exemplary embodiment of the invention, and FIG. 2 is aview showing a pixel shown in FIG. 1.

Referring to FIG. 1, a liquid crystal display 1000 includes an imagedisplay part 300 that displays an image, gate and data drivers 400 and500 that drive the image display part 300, and a timing controller 600that controls a drive of the gate driver 400 and the data driver 500.

The image display part 300 includes a plurality of gate lines G1 to Gn,a plurality of data lines D1 to Dm, and a plurality of pixels PX. Asshown in FIG. 2, the image display part 300 includes a liquid crystaldisplay panel that includes a first substrate 100, a second substrate200 facing the first substrate 100, and a liquid crystal layer 250interposed between the first substrate 100 and the second substrate 200.

The gate lines G1 to Gn and the data lines D1 to Dm are disposed on thefirst substrate 100. The gate lines G1 to Gn are extended in a rowdirection and arranged in a column direction to be parallel to eachother. The data lines D1 to Dm are extended in the column direction andarranged in the row direction to be parallel to each other.

According to an embodiment, each pixel PX is connected to an i-th (i isan integer equal to or greater than 1) gate line Gi and a j-th (j is aninteger equal to or greater than 1) data line Dj and includes a thinfilm transistor Tr, a liquid crystal capacitor Clc, and a storagecapacitor Cst.

The thin film transistor Tr includes a gate electrode connected to thei-th gate line Gi, a source electrode connected to the j-th data lineDj, and a drain electrode connected to the liquid crystal capacitor Clcand the storage capacitor Cst.

The liquid crystal capacitor Clc includes a pixel electrode PE and acommon electrode CE, which are disposed on the first substrate 100, andthe liquid crystal layer 250 functions as a dielectric substance of theliquid crystal capacitor Clc. The pixel electrode PE is electricallyconnected to the drain electrode of the thin film transistor Tr. Thecommon electrode CE receives a reference voltage Vcom.

Each pixel PX includes color filters 230 that are disposed on the secondsubstrate 200 and correspond to the pixel electrode PE, and each of thecolor filters 230 displays one of primary colors including, e.g., red,green, and blue. Alternatively, different from the structure shown inFIG. 2, the color filters 230 are formed on or under the pixel electrodePE of the first substrate 100.

Referring back to FIG. 1, the timing controller 600 receives a pluralityof image signals RGB and a plurality of control signals CS from anoutside source. The timing controller 600 converts a data format of theimage signals RGB to a data format appropriate for an interface betweenthe data driver 500 and the timing controller 600 and provides theconverted image signals R′G′B′ to the data driver 500. The timingcontroller 600 generates a data control signal D-CS, such as an outputstart signal or a horizontal start signal, and a gate control signalG-CS, such as a vertical start signal, a vertical clock signal, or avertical clock bar signal, based on the control signals CS.

The data control signal D-CS is applied to the data driver 500, and thegate control signal G-CS is applied to the gate driver 400.

The gate driver 400 sequentially outputs gate signals in response to thegate control signal G-CS from the timing controller 600. Accordingly,the pixels PX are sequentially scanned by the gate signals on a per-rowbasis.

The data driver 500 converts the image signals R′G′B′ to data voltagesin response to the data control signal D-CS from the timing controller600. The data voltages are applied to the image display part 300.

Thus, each pixel PX is turned on in response to a corresponding gatesignal of the gate signals, and the turned-on pixel PX receives acorresponding data voltage from the data driver 500 to thereby displayan image having a desired gray scale level.

FIG. 3 is a plan view showing a liquid crystal display panel accordingto an exemplary embodiment of the invention, and FIG. 4 is across-sectional view taken along a line I-I′ shown in FIG. 3.

Referring to FIG. 3 and FIG. 4, the liquid crystal display panelincluded in the image display part 300 includes the first substrate 100,the second substrate 200 facing the first substrate 100, and the liquidcrystal layer 250 disposed between the first substrate 100 and thesecond substrate 200.

The first substrate 100 includes a first insulating substrate 110 formedof transparent glass or plastic, a first gate line Gi-1, a second gateline Gi, a first data line Dj-1, and a second data line Dj, which aredisposed on the first insulating substrate 110.

The first and second gate lines Gi-1 and Gi are extended in a firstdirection A1 and spaced apart from each other in a second direction A2substantially perpendicular to the first direction A1. The first andsecond data lines Dj-1 and Dj are extended in the second direction A2and spaced apart from each other in the first direction A1.

The first and second gate lines Gi-1 and Gi are electrically insulatedfrom the first and second data lines Dj-1 and Dj by a gate insulatinglayer 120. The first and second data lines Dj-1 and Dj are covered by afirst protective layer 130. As an example, according to an embodiment,the first protective layer 130 includes at least a silicon oxycarbide(hereinafter, referred to as SiOC) layer.

As shown in FIG. 3, each of the first and second data lines Dj-1 and Djis bent at its center portion to have a symmetrical shape with referenceto a center line CL crossing a center portion between the first andsecond gate lines Gi-1 and Gi. A direction, in which each of the firstand second data lines Dj-1 and Dj is bent, varies from row to row. Forexample, when the first and second data lines Dj-1 and Dj are bentleftward in a first row of pixels, the first and second data lines Dj-1and Dj are bent rightward in a second row of pixels subsequent to thefirst row of pixels.

The first substrate 100 further includes a first storage line Si-1disposed on the first insulating substrate 110 substantially in parallelto the first gate line Gi-1 and a second storage line Si disposed on thefirst insulating substrate 110 substantially in parallel to the secondgate line Gi.

The thin film transistor Tr, the pixel electrode PE, and the commonelectrode CE are further disposed on the first insulating substrate 110.Specifically, the thin film transistor Tr includes a gate electrode GEbranched from the second gate line Gi, a source electrode SEcorresponding to a portion of the second data line Dj, and a drainelectrode DE spaced apart from the source electrode SE above the gateelectrode GE. The drain electrode DE is electrically connected to thepixel electrode PE.

As an example, according to an embodiment, the pixel electrode PEincludes a plurality of branch electrodes PE1, a first connectionportion PE2 connecting first ends of the branch electrodes PE1 to eachother, and a second connection portion PE3 connecting second ends of thebranch electrodes PE1 to each other. The branch electrodes PE1 areextended substantially in the second direction A2 in a space between thefirst and second data lines Dj-1 and Dj and arranged in the firstdirection A1. The branch electrodes PE1 are bent to be symmetrical aboutthe center line CL.

The branch electrodes PE1 are inclined at an angle with respect to thecenter line CL, which is the same or substantially the same as an angleat which the first and second data lines Dj-1 and Dj are inclined withrespect to the center line CL.

The common electrode CE is disposed on or under the pixel electrode PEand has a size corresponding to a pixel area defined by the first andsecond gate lines Gi-1 and Gi and the first and second data lines Dj-1and Dj. As shown in FIG. 4, the common electrode CE is disposed underthe pixel electrode PE. However, the position of the common electrode CEshould not be limited to the lower portion of the pixel electrode PE.Alternatively, the common electrode CE is disposed on the pixelelectrode PE. The common electrode CE faces the pixel electrode PE, witha second protective layer 140 interposed between the common electrode CEand the pixel electrode PE.

As an example, according to an embodiment, a storage electrode TEextended from the first storage line Si-1 is electrically connected tothe common electrode CE. Thus, the common electrode CE receives astorage voltage applied to the first storage line Si-1 as a referencevoltage Vcom.

The second substrate 200 includes a second insulating substrate 210formed of transparent glass or plastic, the color filters 230 disposedon the second insulating substrate 230, and a black matrix 220 disposedbetween the color filters 230. The second substrate 200 is coupled tothe first substrate 100 and faces the first substrate 100. The liquidcrystal layer 250 is interposed between the first and second substrates100 and 200.

When a gate signal is applied to the pixel PX through the second gateline Gi, the thin film transistor Tr is turned on in response to thegate signal. A data voltage passes through the second data line Dj andis applied to the pixel electrode PE through the drain electrode DE ofthe turned-on thin film transistor Tr.

The pixel electrode PE applied with the data voltage forms an electricfield in cooperation with the common electrode CE applied with thereference voltage Vcom, so that the direction of the liquid crystalmolecules of the liquid crystal layer 250, which are disposed on thepixel electrode PE and the common electrode CE, is controlled. Lightpassing through the liquid crystal layer 250 is polarized in variousways according to the direction of the liquid crystal molecules.

Since the pixel electrode PE and the common electrode CE form the liquidcrystal capacitor Clc that employs the liquid crystal layer 250 as thedielectric substance of the liquid crystal capacitor Clc as shown inFIG. 1, the voltage applied to the pixel electrode PE may be maintainedafter the thin film transistor Tr is turned off. The first storage lineSi-1 is formed to overlap the pixel electrode PE and the commonelectrode CE. Accordingly, the first storage line Si-1 together with thepixel electrode PE and the common electrode CE forms the storagecapacitor Cst that uses the gate insulating layer 120 and the first andsecond protective layers 130 and 140 as the dielectric substance of thestorage capacitor Cst as shown in FIG. 1, thereby increasing voltagemaintaining ability of the liquid crystal capacitor Clc.

FIG. 5A to FIG. 5D are plan views showing a manufacturing process of afirst substrate, and FIG. 6A to FIG. 6K are cross-sectional viewsshowing a manufacturing process of the first substrate.

Referring to FIG. 5A and FIG. 6A, a first metal layer is formed on thefirst insulating substrate 110 and patterned to thereby form the firstand second gate lines Gi-1 and Gi and the first and second storage linesSi-1 and Si. According to an embodiment, the first metal layer includesan aluminum-based metal, such as aluminum (Al) or aluminum alloys, asilver-based metal, such as silver (Ag) or silver alloys, a copper-basedmetal, such as copper (Cu) or copper alloys, a molybdenum-based metal,such as molybdenum (Mo) or molybdenum alloys, chromium (Cr), tantalum(Ta), or titanium (Ti). According to an embodiment, the first metallayer has a multi-layered structure of two or more conductive layershaving different properties from each other.

A portion of each of the first and second gate lines Gi-1 and Gi isextended and forms the gate electrode GE, and a portion of each of thefirst and second storage lines Si-1 and Si is extended and forms thestorage electrode TE.

As shown in FIG. 6B, the first and second gate lines Gi-1 and Gi and thefirst and second storage lines Si-1 and Si are covered by the gateinsulating layer 120. According to an embodiment, the gate insulatinglayer 120 is formed of silicon nitride (SiNx) or silicon oxide (SiOx).

A semiconductor layer 125 is formed of hydrogenated amorphous silicon orpolysilicon on the gate insulating layer 120. The semiconductor layer125 is disposed above the gate electrode GE.

First and second ohmic contact layers 126 and 127 are formed on thesemiconductor layer 125. The first and second ohmic contact layers 126and 127 are formed of n+ hydrogenated amorphous silicon doped with ahigh-concentration of n-type impurity, e.g., phosphor, or silicide. Thefirst and second ohmic contact layers 126 and 127 are disposed on thesemiconductor layer 125 and spaced apart from each other.

Referring to FIG. 5B and FIG. 6C, a second metal layer is formed on thegate insulating layer 120 and the first and second ohmic contact layers126 and 127 and patterned to thereby form the first and second datalines Dj-1 and Dj. The second metal layer includes a refractory metal,such as molybdenum, chromium, tantalum, titanium, or an alloy thereof.

A portion of the first and second data lines Dj-1 and Dj, which facesthe gate electrode GE, is defined as the source electrode SE andcontacts the first ohmic contact layer 126. The drain electrode DE isdisposed above the gate electrode GE to be spaced apart from the sourceelectrode SE and contacts the second ohmic contact layer 127.

As shown in FIG. 6D, the first and second data lines Dj-1 and Dj andsource and drain electrodes SE and DE are covered by the firstprotective layer 130. The first protective layer 130 includes a bufferlayer 131 and an SiOC layer 132 that are sequentially stacked. Accordingto an embodiment, the buffer layer 131 is formed of an inorganicinsulating material, such as silicon nitride SiNx or silicon oxide SiOx.The SiOC layer 132 is disposed on the buffer layer 131.

The buffer layer 131 and the SiOC layer 132 are deposited by a chemicalvapor deposition process. The SiOC layer 132 may withstand a temperatureof about 370 degrees during the chemical vapor deposition process. Forexample, the SiOC layer 132 has a processing temperature higher than aprocessing temperature of the organic insulating material. The organicinsulating material has a processing temperature of about 220 degrees orless. As an example, according to an embodiment, the chemical vapordeposition process for forming the SiOC layer 132 is performed in atemperature range from about 270 degrees to about 370 degrees.

The SiOC layer 132 has a superior heat-resistance when compared with theorganic layer, and thus deterioration of display quality, which iscaused by afterimages, may be prevented.

The SiOC layer 132 has a faster deposition speed than a deposition speedof the inorganic insulating material. The deposition speed of theinorganic insulating material is about 1000 angstroms per minute. Forexample, when the buffer layer 131 is formed of silicon nitride, thedeposition of the buffer layer 131 is performed at a rate of about 2000angstroms to about 5000 angstroms in about two or about three minutes inthe chemical vapor deposition process. The deposition of the SiOC layer132 is conducted at about two or about three micrometers in about two orabout three minutes in the chemical vapor process. Accordingly, in theprocess of forming the first protective layer 130 having a thickness ofabout two or about three micrometers, it results in faster processingtime to form the first protective layer 130 using the SiOC layer 132rather than using silicon nitride or silicon oxide.

Further, the SiOC layer 132 is formed under a stress of about 15 Mpa,which is relatively lower than a stress under which an organicinsulating layer is formed. Accordingly, the deposited SiOC layer 132may be prevented from peeling off other layers, and an adhesive forcebetween the SiOC layer 132 and the other layers may be prevented frombeing lowered. A thickness uniformity of the SiOC layer 132 formed bythe deposition process is above about 6.2%, which is relatively higherthan a thickness uniformity of the organic insulating layer, e.g., about3%. A thickness uniformity is obtained by dividing a value, which isobtained by subtracting a minimum thickness of a layer to be depositedfrom a maximum thickness of the layer to be deposited, by a value whichis obtained by adding the maximum thickness and the minimum thickness.

The SiOC layer 132 results in faster processing time, lower layerstress, and greater thickness uniformity than the organic insulatinglayer. The SiOC layer 132 is deposited to a thickness corresponding tothe organic insulating layer during a processing time shorter than aprocessing time applied to the inorganic insulating material. The SiOClayer 132 has a dielectric constant from about 2.8 to about 3.0

The protective layer 130 includes the SiOC layer 132 and thus the sameor substantially the same effect as is obtained when an organic layer isemployed as the first protective layer 130 may be achieved. Since theSiOC layer 132 is under relatively a low stress and has a relativelyhigh processing temperature and high thickness uniformity, adeterioration of display quality, which is caused by afterimages, may beprevented.

Referring to FIG. 6E, a photosensitive resin 135 is formed on the firstprotective layer 130. The photosensitive resin 135 is patterned by aphotolithography process, and the first protective layer 130 is etchedusing the patterned photosensitive resin 135.

As an example, according to an embodiment, the photosensitive resin 135includes a positive photosensitive resin. For example, a first exposuremask 136 is disposed on the photosensitive resin 135. The first exposuremask 136 includes first and second openings 136 a and 136 b thatrespectively correspond to portions of the first protective layer 130,which are to be removed. When the photosensitive resin 135 is exposedand developed after the first exposure mask 136 is disposed, aphotosensitive resin pattern is formed and exposes the portions of thefirst protective layer 130. When the first protective layer 130 isetched using the photosensitive resin pattern as an etch mask, first andsecond contact holes 130 a and 130 b are formed through the firstprotective layer 130 as shown in FIG. 6F.

More specifically, the first contact hole 130 a is formed by removingportions of the buffer layer 131 and the SiOC layer 132 to expose thedrain electrode DE of the thin film transistor Tr. The second contacthole 130 b is formed by removing portions of the gate insulating layer120, the buffer layer 131, and the SiOC layer 132 to expose the storageelectrode TE.

In FIG. 6E, the positive photosensitive resin 135 has been described asan example, but alternatively, the photosensitive resin 135 includes anegative photosensitive resin 135. When the SiOC layer 132 is patternedusing the positive photosensitive resin, the first and second contactholes 130 a and 130 b may be reduced in diameter compared with when theSiOC layer 132 is patterned using the negative photosensitive resin. Inother words, when the patterning of the SiOC layer 132 is performedusing the positive photosensitive resin, the size of the first andsecond contact holes 130 a and 130 b may be controlled. When the size ofthe first and second contact holes 130 a and 130 b decreases, anaperture ratio of the pixel PX is increased, and thus a transmittance ofthe liquid crystal display 1000 may be increased.

Referring to FIG. 5C and FIG. 6G, a first transparent conductive layeris formed on the first protective layer 130. The first transparentconductive layer is formed of a transparent conductive material, such asindium tin oxide. The first transparent conductive layer is patterned tothereby form the common electrode CE. The common electrode CE iselectrically connected to the storage electrode TE through the secondcontact hole 130 b. Accordingly, the common electrode CE receives astorage voltage as a reference voltage Vcom (as shown in FIG. 2) throughthe storage electrode TE.

Referring to FIG. 6H, the common electrode CE is covered by the secondprotective layer 140. The second protective layer 140 is formed of aninorganic insulating material, such as silicon nitride or silicon oxide,or SiOC material.

Referring to FIG. 6I, a photosensitive resin 143 is formed on the secondprotective layer 140. The photosensitive resin 143 is patterned by aphotolithography process, and the second protective layer 140 is etchedusing the patterned photosensitive resin.

Specifically, a second exposure mask 145 is disposed on thephotosensitive resin 143. The second exposure mask 145 includes a thirdopening 145 a that corresponds to a portion of the second protectivelayer 140, which is to be removed. When the photosensitive resin 143 isexposed and developed after the second exposure mask 145 is disposed onthe photosensitive resin 143, a photosensitive resin pattern is formedto thereby expose the portion of the second protective layer 140. Whenthe second protective layer 140 is etched using the photosensitive resinpattern as an etch mask, a third contact holes 140 a is formed throughthe second protective layer 140 as shown in FIG. 6J.

Specifically, the third contact hole 140 a is formed by removing aportion of the second protective layer 140 and corresponds to the firstcontact hole 130 a that exposes the drain electrode DE of the thin filmtransistor Tr.

Referring to FIG. 5D and FIG. 6K, a second transparent conductive layeris formed on the second protective layer 140. The second transparentconductive layer is formed of a transparent conductive material, such asindium tin oxide. The second transparent conductive layer is patternedto thereby form the pixel electrode PE. The pixel electrode PE iselectrically connected to the drain electrode DE through the first andthird contact holes 130 a and 140 a. Accordingly, the pixel electrode PEreceives a data voltage through the drain electrode DE.

As shown in FIG. 6K, the pixel electrode PE includes the branchelectrodes PE1, the first connection portion PE2 connecting the firstend portions of the branch electrodes PE1 to each other, and the secondconnection portion PE3 connecting the second end portions of the branchelectrodes PE1 to each other.

FIG. 7 is a cross-sectional view showing a liquid crystal display panelaccording to an exemplary embodiment of the invention. The liquidcrystal display panel shown in FIG. 7 has the same or substantially thesame structure and function as those of the liquid crystal display paneldescribed in connection with FIG. 4 except for the structure of thefirst protective layer.

Referring to FIG. 7, a liquid crystal display panel 300 includes a firstprotective layer 130 that is disposed on the gate insulating layer 120and covers the first and second data lines Dj-1 and Dj and the sourceand drain electrodes SE and DE.

The first protective layer 130 includes a SiOC layer 132 and a cappinglayer 133 that are sequentially stacked. The SiOC layer 132 has athickness of about two or about three micrometers, and the capping layer133 is disposed on the SiOC layer 132. The capping layer 133 has athickness smaller than a thickness of the SiOC layer 132. As an example,according to an embodiment, the capping layer 133 includes siliconnitride or silicon oxide.

The common electrode CE is disposed on the first protective layer 130.The first and second data lines Dj-1 and Dj are spaced apart from thecommon electrode CE by the SiOC layer 132 and the capping layer 133 ofthe first protective layer 130, so that the signal interference betweenthe common electrode CE and the first and second data lines Dj-1 and Djmay be reduced.

FIG. 8 is a cross-sectional view showing a liquid crystal display panelaccording to an exemplary embodiment of the invention. The liquidcrystal display panel shown in FIG. 8 has the same or substantially thesame structure and function as those of the liquid crystal display paneldescribed in connection with FIG. 4 except for the structure of thefirst protective layer.

Referring to FIG. 8, a liquid crystal display panel 300 includes a firstprotective layer 130 that is disposed on the gate insulating layer 120and covers the first and second data lines Dj-1 and Dj and the sourceand drain electrodes SE and DE.

The first protective layer 130 includes a buffer layer 131, a SiOC layer132, and a capping layer 133 that are sequentially stacked. The SiOClayer 132 has a thickness of about two or about three micrometers, andthe buffer layer 131 and the capping layer 133 have a thickness smallerthan a thickness of the SiOC layer 132. As an example, according to anembodiment, the buffer layer and the capping layer 133 include siliconnitride or silicon oxide.

The common electrode CE is disposed on the first protective layer 130.The first and second data lines Dj-1 and Dj are spaced apart from thecommon electrode CE by the buffer layer 131, the SiOC layer 132, and thecapping layer 133 of the first protective layer 130, so that the signalinterference between the common electrode CE and the first and seconddata lines Dj-1 and Dj may be reduced.

Although the exemplary embodiments of the present invention have beendescribed, it is understood that the present invention should not belimited to these exemplary embodiments but various changes andmodifications can be made by one ordinary skilled in the art within thespirit and scope of the present invention as hereinafter claimed.

What is claimed is:
 1. A liquid crystal display comprising: a firstsubstrate which includes a plurality of pixels; a second substratefacing the first substrate; and a liquid crystal layer between the firstsubstrate and the second substrate, at least one of the pixelscomprising: a thin film transistor on a first insulating substrate; afirst protective layer which covers the thin film transistor andincludes a silicon oxycarbide (SiOC) layer; a first electrode on thefirst protective layer; a second protective layer which covers the firstelectrode; and a second electrode disposed on the second protectivelayer.
 2. The liquid crystal display of claim 1, wherein the firstprotective layer further comprises a capping layer that covers the SiOClayer.
 3. The liquid crystal display of claim 2, wherein the cappinglayer comprises silicon nitride or silicon oxide.
 4. The liquid crystaldisplay of claim 1, wherein the first protective layer further comprisesa buffer layer between the thin film transistor and the SiOC layer. 5.The liquid crystal display of claim 4, wherein the first protectivelayer further comprises a capping layer that covers the SiOC layer. 6.The liquid crystal display of claim 5, wherein the buffer layer and thecapping layer comprise silicon nitride or silicon oxide.
 7. The liquidcrystal display of claim 1, wherein the SiOC layer has a thickness equalto or larger than about two micrometers.
 8. The liquid crystal displayof claim 1, wherein the SiOC layer has a dielectric constant from about2.8 to about 3.0.
 9. The liquid crystal display of claim 1, wherein thesecond protective layer comprises silicon nitride or silicon oxide. 10.The liquid crystal display of claim 1, wherein the first and secondelectrodes comprise a transparent conductive material.
 11. The liquidcrystal display of claim 1, wherein the first substrate comprises: aplurality of gate lines on the first insulating substrate; a pluralityof data lines insulated from the gate lines, the data lines crossing thegate lines; and a plurality of storage lines extended in parallel orsubstantially in parallel with the gate lines.
 12. The liquid crystaldisplay of claim 11, wherein the thin film transistor comprises a gateelectrode extended from a corresponding gate line of the gate lines, asource electrode extended from a corresponding data line of the datalines, and a drain electrode electrically connected to the secondelectrode, and wherein at least one of the pixels further comprises astorage electrode extended from a corresponding storage line of thestorage lines.
 13. The liquid crystal display of claim 12, wherein thefirst electrode is electrically connected to the storage electrode, andthe second electrode is electrically connected to the drain electrode ofthe thin film transistor.
 14. A method of manufacturing a liquid crystaldisplay comprising a first substrate including a plurality of pixels, asecond substrate facing the first substrate, and a liquid crystaldisplay between the first and second substrates, the method comprising:forming a thin film transistor on a first insulating substrate; forminga first protective layer including a SiOC layer that covers the thinfilm transistor; forming a first electrode on the first protectivelayer; forming a second protective layer that covers the firstelectrode; and forming a second electrode on the second protectivelayer.
 15. The method of claim 14, wherein the first protective layer isformed by a chemical vapor deposition process at a temperature fromabout 270 degrees to about 370 degrees.
 16. The method of claim 14,wherein the first substrate comprises: a plurality of gate lines on thefirst insulating substrate; a plurality of data lines insulated from thegate lines, the data lines crossing the gate lines; and a plurality ofstorage lines extended in parallel or substantially in parallel with thegate lines.
 17. The method of claim 16, wherein the thin film transistorcomprises a gate electrode extended from a corresponding gate line ofthe gate lines, a source electrode extended from a corresponding dataline of the data lines, and a drain electrode electrically connected tothe second electrode, and wherein at least one of the pixels furthercomprises a storage electrode extended from a corresponding storage lineof the storage lines.
 18. The method of claim 17, wherein forming thefirst substrate further comprises forming a first contact hole throughthe first protective layer to expose the drain electrode and a secondcontact hole through the first protective layer to expose the storageelectrode.
 19. The method of claim 18, wherein forming the first andsecond contact holes comprises: forming a photosensitive resin on thefirst protective layer; patterning the photosensitive resin; etching thefirst protective layer using the patterned photosensitive resin as amask to form the first and second contact holes; and removing thephotosensitive resin.
 20. The method of claim 19, wherein thephotosensitive resin includes a positive type photosensitive resin. 21.A display apparatus comprising: a plurality of data lines; an SiOC layeron the plurality of data lines; a common electrode on the SiOC layer; aprotective layer on the common electrode; and pixel electrode on theprotective layer.
 22. The display apparatus of claim 21, furthercomprising a capping layer between the SiOC layer and the commonelectrode.
 23. The display apparatus of claim 22, further comprising abuffer layer between the plurality of data lines and the SiOC layer. 24.The display apparatus of claim 21, wherein the SiOC layer has athickness of about two micrometers to about three micrometers.